This invention relates to asynchronous circuits, and in particular to an improved asynchronous circuit having zero overhead in forward latency.
Advances in semiconductor fabrication technology continually allow increasing numbers of logic gates to be placed on a single integrated circuit and permit operation of such circuits at speeds greater than prior generations of circuits. Two known methodologies for the design of such circuits are synchronous and asynchronous. Synchronous designs provide a global clock signal which causes all of the circuitry on the integrated circuit chip to operate in lockstep. Asynchronous designs use local control to determine when local gates operate, and the local gates do not necessarily operate in synchrony with the rest of the integrated circuit chip. As such, asynchronous designs eliminate the difficulty of distributing a clock "globally" across the integrated circuit, and also potentially offer improved speed, lower power consumption, and other benefits.
Asynchronous circuits can be broadly characterized as self-timed and timed. Self-timed asynchronous circuits, often referred to as delay insensitive circuits, use a "hand shake" between data and control circuits to assure that the control does not request operations until the appropriate data is available. Timed circuits attempt to match the delays of the control and data circuits so that the control circuit does not activate until the data is ready. As a result, self-timed circuits are more robust because they do not depend upon accurate matching of delays, a difficult phenomenon over the wide range of performance resulting from tolerances in integrated circuit manufacturing processes. In self-timed circuits, the data signals indicate not only the value of the data, but also its validity. This enables the control system to assure data validity before processing the data. One technique for achieving this is to encode a data bit using two signals, referred to as dual rail signaling. If both signals are low, the data is invalid. If the first signal is high and the second low, the data can be considered high, while if the second is high and the first low, the data can be considered low. A condition of both signals being high is not permitted.
Prior self-timed domino circuits are generally discussed and disclosed in a commonly assigned copending patent application "Apparatus and Methods for High Throughput Self-Timed Domino Circuits," Ser. No. 09/305,904, filed May 5, 1999 by David Harris and William Coates.